1. Field of the Invention
The present invention relates generally to an optical disk apparatus, and in particular to memory allocation within an Optical disk apparatus.
2. Description of the Related Art
Optical disk apparatus have hitherto used a digital signal processor ("DSP") in order digitally process servo signals through the execution of programs or routines, which are also referred to as software or firmware.
In software servo processing, a focusing error signal and a tracking error signal contained within an output signal of a quadrant diode type of optical pickup are converted by an analog-to-digital ("A/D") converting circuit into digital signals. These digital signals are supplied through a bus line to a DSP. The DSP then processes these digital signals supplied thereto in accordance with a predetermined routine or program in some suitable signal processing fashion, such as a phase compensation or the like. The processed digital signals are supplied through a digital-to-analog ("D/A") converting circuit and a driver to a focusing actuator and to a tracking actuator of the optical pickup.
In a conventional optical disk apparatus in which the DSP executes the software servo processing, the DSP is also utilized to execute processing other than the servo processing, such as system control or the like. In such a conventional optical disk apparatus, servo processing has a higher interrupt processing priority. Therefore, at the beginning of the interrupt processing (interrupt routine), data in the internal registers of the DSP are stored in and saved in a data RAM of the DSP. At the completion of interrupt processing, data is returned to the internal registers from the data RAM.
A typical digital signal processor used in conventional optical disk apparatus is one manufactured and sold by the Motorola, Inc., Semiconductor Products Sector, 3102 Noah 56th Street, Phoenix, Ariz. 85018 under the model designation DSP56001. The DSP56001 is a24-bit fixed-point general purpose digital signal processor which features three single-cycle execution units, namely, a data arithmetic logic unit, an address arithmetic unit and a program controller, all of which operate in parallel at instruction speeds of up to 16.5 MHz. The DSP56001 also contains an on-chip program random access memory (RAM). Using such a DSP, a time or period corresponding to 68 steps is required in order to save and return data because this DSP contains a total of 34 internal registers. In further detail, assuming an operation speed of the DSP is 100 nsec/step, and a servo signal sampling rate of 30 kHz, then 333 steps (1/30 kHz/100 nsec) of the program at maximum can be executed in one interrupt routine. As a consequence, about 20% of the time is consumed in order to save and return data from and to the internal registers.
If 200 steps are consumed to effect servo signal processing, then only 65 steps {333-(200+68)}can be used to execute signal processing other than the servo signal processing, such as system control processing or the like within one sampling period and a time of only 6.5 .mu.s is available. In worst cases, it becomes necessary to utilize a microcomputer in addition to the DSP, in order to execute system control processing or the like.
Therefore, it would be desireable to provide a method and apparatus for more efficient utilization of a digital signal processor by reducing the number of steps required to process and store information such as a servo signal information.